A timing generator LSI for supplying a clock signal to an LSI tester is provided with a variable delay circuit and outputs a clock signal with a phase according to a test timing. Since a timing generator circuit is equipped with a plurality of variable delay circuits to sufficiently ensure the accuracy and the variable delay range of a clock signal to be output therefrom, the timing generator circuit is a complicated one. The delay control circuit can perform a small current control by using a digital-to-analog conversion circuit (hereinafter referred to as DAC) to improve the accuracy of delay and save electricity. An increase in degree of integration also increases the number of variable delay circuits which can be mounted on one LSI. Accordingly, the number of variable delay circuits mounted on one timing generator LSI reaches about several hundreds.
A ring oscillator is formed of variable delay circuits to measure its oscillation frequency, ensuring the operation of circuits in such a timing generator LSI. JP-A-2000-180514 discusses an example in which, although the document has its purpose to calibrate the phase of an output clock signal, a signal output to the terminal of a signal transmission route is fed back to the starting end thereof to form a closed loop oscillation circuit, which is used to adjust timing.
US2007/0091701 discloses a test method using the DAC. US2007/0091701 discusses that the operation confirmation of a transistor for controlling the current path of the DAC is performed by a functional test; however, the output current and voltage are outputted to an external tester.